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| a FEATURES 44 V Supply Maximum Ratings 15 V Analog Signal Range Low On Resistance (<35 ) Ultralow Power Dissipation (35 W) Fast Switching Times tON <175 ns tOFF <145 ns TTL/CMOS Compatible Plug-In Replacement for DG411/DG412/DG413 APPLICATIONS Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Battery Powered Systems Sample Hold Systems Communication Systems LC2MOS Precision Quad SPST Switches ADG411/ADG412/ADG413 FUNCTIONAL BLOCK DIAGRAMS S1 IN1 D1 S2 IN2 IN2 D2 S3 IN3 D3 S4 IN4 D4 S1 IN1 D1 S2 IN2 D2 S3 D3 S4 IN4 D4 SWITCHES SHOWN FOR A LOGIC "1" INPUT IN4 D4 D3 S4 IN1 D1 S2 D2 S3 S1 ADG411 IN3 ADG412 ADG413 IN3 GENERAL DESCRIPTION The ADG411, ADG412 and ADG413 are monolithic CMOS devices comprising four independently selectable switches. They are designed on an enhanced LC2MOS process which provides low power dissipation yet gives high switching speed and low on resistance. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. Fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments. The ADG411, ADG412 and ADG413 contain four independent SPST switches. The ADG411 and ADG412 differ only in that the digital control logic is inverted. The ADG411 switches are turned on with a logic low on the appropriate control input, while a logic high is required for the ADG412. The ADG413 has two switches with digital control logic similar to that of the ADG411 while the logic is inverted on the other two switches. Each switch conducts equally well in both directions when ON and each has an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS 1. Extended Signal Range The ADG411, ADG412 and ADG413 are fabricated on an enhanced LC 2MOS, giving an increased signal range which extends fully to the supply rails. 2. Ultralow Power Dissipation 3. Low RON 4. Break-Before-Make Switching This prevents channel shorting when the switches are configured as a multiplexer. 5. Single Supply Operation For applications where the analog signal is unipolar, the ADG411, ADG412 and ADG413 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and will remain functional with single supplies as low as +5 V. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998 ADG411/ADG412/ADG413-SPECIFICATIONS1 Dual Supply Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF (VDD = +15 V 10%, VSS = -15 V 10%, VL = +5 V 10%, GND = 0 V, unless otherwise noted) B Version -40 C to +25 C +85 C VDD to VSS 25 35 0.1 0.25 0.1 0.25 0.1 0.4 45 T Version -55 C to +25 C +125 C Units Test Conditions/Comments 25 35 0.1 0.25 0.1 0.25 0.1 0.4 VDD to VSS V typ 45 max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ VD = 8.5 V, IS = -10 mA; VDD = +13.5 V, VSS = -13.5 V VDD = +16.5 V, VSS = -16.5 V VD = 15.5 V, VS = 15.5 V; Test Circuit 2 VD = 15.5 V, VS = 15.5 V; Test Circuit 2 VD = VS = 15.5 V; Test Circuit 3 5 5 10 2.4 0.8 20 20 40 2.4 0.8 0.005 0.5 0.005 0.5 VIN = VINL or VINH 110 175 100 145 110 175 100 145 25 Break-Before-Make Time Delay, tD 25 (ADG413 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ISS IL 0.0001 1 0.0001 1 0.0001 1 5 68 85 9 9 35 5 68 85 9 9 35 pC typ dB typ dB typ pF typ pF typ pF typ RL = 300 , C L = 35 pF; VS = 10 V; Test Circuit 4 RL = 300 , C L = 35 pF; VS = 10 V; Test Circuit 4 RL = 300 , C L = 35 pF; VS1 = VS2 = +10 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital Inputs = 0 V or 5 V 5 5 5 0.0001 1 0.0001 1 0.0001 1 5 5 5 A typ A max A typ A max A typ A max NOTES 1 Temperature ranges are as follows: B Versions: -40 C to +85C; T Versions: -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. -2- REV. A ADG411/ADG412/ADG413 Single Supply (V Parameter ANALOG SIGNAL RANGE RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF DD = +12 V 10%, VSS = 0 V, VL = +5 V B Version -40 C to +25 C +85 C 0 V to VDD 40 80 0.1 0.25 0.1 0.25 0.1 0.4 100 10%, GND = 0 V, unless otherwise noted) T Version -55 C to +25 C +125 C 40 80 0.1 0.25 0.1 0.25 0.1 0.4 Units Test Conditions/Comments 0 < VD = 8.5 V, IS = -10 mA; VDD = +10.8 V VDD = +13.2 V VD = 12.2/1 V, VS = 1/12.2 V; Test Circuit 2 VD = 12.2/1 V, VS = 1/12.2 V; Test Circuit 2 VD = VS = +12.2 V/+1 V; Test Circuit 3 0 V to VDD V typ 100 max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ 5 5 10 2.4 0.8 20 20 40 2.4 0.8 0.005 0.5 0.005 0.5 VIN = VINL or VINH 175 250 95 125 175 250 95 125 25 Break-Before-Make Time Delay, tD 25 (ADG413 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD IL 0.0001 1 0.0001 1 25 68 85 9 9 35 25 68 85 9 9 35 pC typ dB typ dB typ pF typ pF typ pF typ RL = 300 , C L = 35 pF; VS = +8 V; Test Circuit 4 RL = 300 , C L = 35 pF; VS = +8 V; Test Circuit 4 RL = 300 , C L = 35 pF; VS1 = VS2 = +10 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +13.2 V Digital Inputs = 0 V or 5 V 5 5 0.0001 1 0.0001 1 5 5 A typ A max A typ A max VL = +5.25 V NOTES 1 Temperature ranges are as follows: B Versions: -40 C to +85C; T Versions: -55C to +125C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. Truth Table (ADG411/ADG412) Truth Table (ADG413) ADG411 In 0 1 ADG412 In 1 0 Switch Condition ON OFF Logic 0 1 Switch 1, 4 OFF ON Switch 2, 3 ON OFF REV. A -3- ADG411/ADG412/ADG413 ABSOLUTE MAXIMUM RATINGS 1 (TA = +25C unless otherwise noted) TERMINOLOGY VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V VL to GND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Analog, Digital Inputs2 . . . . . . . . . . . VSS -2 V to V DD +2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 76C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300C Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 77C/W TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 115C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 35C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. VDD VSS VL GND S D IN RON IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) CD, CS (ON) tON tOFF tD Crosstalk Off Isolation Charge Injection Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to GND. Logic power supply (+5 V). Ground (0 V) reference. Source terminal. May be an input or output. Drain terminal. May be an input or output. Logic control input. Ohmic resistance between D and S. Source leakage current with the switch "OFF." Drain leakage current with the switch "OFF." Channel leakage current with the switch "ON." Analog voltage on terminals D, S. "OFF" switch source capacitance. "OFF" switch drain capacitance. "ON" switch capacitance. Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. "OFF" time or "ON" time measured between the 90% points of both switches, when switching from one address state to another. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an "OFF" switch. A measure of the glitch impulse transferred from the digital input to the analog output during switching. PIN CONFIGURATION (DIP/SOIC) ORDERING GUIDE Model l Temperature Range -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C Package Option N-16 R-16A Q-16 RU-16 N-16 R-16A Q-16 N-16 R-16A 2 ADG411BN ADG411BR ADG411TQ ADG411BRU ADG412BN ADG412BR ADG412TQ ADG413BN ADG413BR IN1 1 D1 2 S1 3 VSS 4 16 15 IN2 D2 S2 VDD TOP VIEW GND 5 (Not to Scale) 12 VL S4 6 11 S3 13 ADG411 ADG412 ADG413 14 D4 7 IN4 8 10 9 D3 IN3 NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers. 2 N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); RU= Thin Shrink Small Outline (TSSOP); Q = Cerdip. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG411/ADG412/ADG413 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE -4- REV. A ADG411/ADG412/ADG413 Typical Performance Graphs 50 TA = +25 C VL = +5V 40 VDD = +5V VSS = -5V 30 RON - VDD = +12V VSS = -12V RON - VDD = +10V VSS = -10V 20 30 40 VDD = +5V VSS = 0V VDD = +10V VSS = 0V VDD = +12V VSS = 0V 50 TA = +25 C VL = +5V 20 10 VDD = +15V VSS = -15V 0 -20 10 VDD = +15V VSS = 0V 0 -10 0 10 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 20 0 5 10 15 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 20 Figure 1. On Resistance as a Function of VD (V S) Dual Supplies Figure 4. On Resistance as a Function of VD (VS ) Single Supply 50 VDD = +15V VSS = -15V VL = +5V 100mA VDD = +15V VSS = -15V VL = +5V 4 SW 1 SW 40 10mA 1mA 30 ISUPPLY RON - 100 A I+, I- +125 C 20 +85 C +25 C 10 1A 10 A IL 0 -20 -10 0 10 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 20 100nA 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 2. On Resistance as a Function of VD (V S) for Different Temperatures Figure 5. Supply Current vs. Input Switching Frequency 10 VDD = +15V VSS = -15V VL = +5V LEAKAGE CURRENT - nA 1 VS = VD = 0.1 15V 15V IS (OFF) LEAKAGE CURRENT - nA 0.04 0.02 VDD = +15V VSS = -15V TA = +25 C VL = +5V ID (ON) IS (OFF) 0.00 ID (OFF) 0.01 ID (ON) ID (OFF) -0.02 0.001 100 1k 10k 100k 1M FREQUENCY - Hz 10M 10M -0.04 -20 0 10 -10 VD OR VS - DRAIN OR SOURCE VOLTAGE - V 20 Figure 3. Leakage Currents as a Function of Temperature Figure 6. Leakage Currents as a Function of V D (V S) REV. A -5- ADG411/ADG412/ADG413 120 VDD = +15V VSS = -15V VL = +5V 100 OFF ISOLATION - dB APPLICATION 80 Figure 9 illustrates a precise, fast, sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an AD711. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH. Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG411/ADG412/ ADG413 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 30 V/s. 60 40 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 7. Off Isolation vs. Frequency 110 VDD = +15V VSS = -15V VL = +5V 100 CROSSTALK - dB A second switch, SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differential effect on the op amp AD711, which will minimize charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the 10 V input range. Both the acquisition and settling times are 850 ns. +15V +5V 2200pF 90 80 SW1 +15V 70 VIN AD845 -15V 1k 10k 100k FREQUENCY - Hz 1M 10M S S SW2 D D RC 75 CC 1000pF CH 2200pF +15V AD711 VOUT -15V 60 100 ADG411 ADG412 ADG413 Figure 8. Crosstalk vs. Frequency -15V Figure 9. Fast, Accurate Sample-and-Hold -6- REV. A ADG411/ADG412/ADG413 Test Circuits IDS V1 IS (OFF) A VS ID (OFF) S D A VD VS S D ID (ON) A VD S VS D RON = V1/IDS Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage +15V 0.1 F +5V 0.1 F 3V VDD S VS VL D RL 300 VOUT CL 35pF VIN ADG411 3V 50% 50% VIN ADG412 50% 90% 50% 90% IN GND VSS VOUT 0.1 F -15V tON tOFF Test Circuit 4. Switching Times +15V 0.1 F +5V 0.1 F 3V VIN D1 D2 RL2 300 VOUT2 CL2 35pF VOUT2 0V 90% 90% RL1 300 CL1 35pF VOUT1 VOUT1 0V VDD VS1 VS2 S1 S2 IN1, IN2 GND VL 0V 50% 90% 50% 90% VIN VSS 0.1 F -15V tD tD Test Circuit 5. Break-Before-Make Time Delay +15V VDD RS VS S +5V VL D VOUT CL 10nF VSS -15V VOUT QINJ = CL VOUT VOUT VIN 3V IN GND Test Circuit 6. Charge Injection REV. A -7- ADG411/ADG412/ADG413 +15V 0.1 F +5V 0.1 F +15V 0.1 F +5V 0.1 F VDD S VL D RL 50 VOUT VS VOUT RL 50 VDD S VL D 50 VS VIN IN D GND S VSS GND VSS VIN2 NC 0.1 F -15V 0.1 F -15V CHANNEL TO CHANNEL CROSSTALK = 20 LOG VS/VOUT Test Circuit 7. Off Isolation Test Circuit 8. Channel-to-Channel Crosstalk MECHANICAL INFORMATION Dimensions are shown in inches and (mm). 16-Lead Cerdip (Q-16) 0.005 (0.13) MIN 16 16-Lead SOIC (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 1 9 8 0.080 (2.03) MAX 9 0.310 (7.87) 0.220 (5.59) 1 8 0.1574 (4.00) 0.1497 (3.80) 0.320 (8.13) 0.290 (7.37) 0.0098 (0.25) 0.0040 (0.10) 0.015 (0.38) 0.008 (0.20) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) PIN 1 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45 0.0099 (0.25) 0.100 (2.54) BSC 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15 0 0.0500 SEATING (1.27) PLANE BSC 0.0192 (0.49) 0.0138 (0.35) 8 0.0099 (0.25) 0 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 16-Lead Plastic DIP (Narrow) (N-16) 0.840 (21.34) 0.745 (18.92) 16 1 9 8 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.177 (4.50) 0.169 (4.30) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.256 (6.50) 0.246 (6.25) 0.325 (8.26) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 16 9 1 8 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) 0.006 (0.15) 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0256 SEATING (0.65) PLANE BSC 8 0 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) -8- REV. A PRINTED IN U.S.A. C1748a-3-2/98 VIN1 |
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